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lt4250l/lt4250h 1 4250lhfa typical application description negative 48v hot swap controller voltage step on input supply l , lt, ltc and ltm are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. features applications n allows safe board insertion and removal from a live C48v backplane n circuit breaker immunity to voltage steps and current spikes n programmable inrush and short-circuit current limits n pin compatible with lt1640l/lt1640h n operates from C18v to C80v n programmable overvoltage protection n programmable undervoltage lockout n power good control output n bell-core compatible on /off threshold n central office switching n C48v distributed power systems n negative power supply control the lt ? 4250l/lt4250h are 8-pin, negative 48v hot swap? controllers that allow a board to be safely inserted and removed from a live backplane. inrush current is limited to a programmable value by controlling the gate voltage of an external n-channel pass transistor. the pass tran- sistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. a programmable current limit protects the system against shorts. after a 500s timeout the current limit activates the electronic circuit breaker. the pwrgd (lt4250l) or pwrgd (lt4250h) signal can be used to directly enable a power module. the lt4250l is designed for modules with a low enable input and the lt4250h for modules with a high enable input. the lt4250l/lt4250h are available in 8-pin pdip and so packages v ee v dd lt4250l sense c1 ? 470nf 25v c2 ? 15nf 100v c3 0.1f 100v c4 100f 100v q1 irf530 r2 10 5% r3 ? 1k, 5% r4 ? 549k 1% r6 ? 10k 1% r1 ? 0.02 5% 4 ov C48v rtn C48v rtn (short pin) 3 2 ov = 71v * * diodes inc. smat70a ? these components are application specific and must be selected based upon operating conditions and desired performance. see applications information. uv = 38.5v uv 56 8 7 1 gate drain pwrgd 4250 ta01a v out + sense + trim sense C v out C v in C on /off lucent jw050a1-e v in + 2 9 5v 8 7 6 5 1 4 + c5 100f 16v + C48v input 1 C48v input 2 uv release at 43v r5 ? 6.49k 1% 0.1f 10v v ee and drain 20v/div i d (q1) 5a/div 500s/div 4250 ta01b
lt4250l/lt4250h 2 4250lhfa pin configuration absolute maximum ratings supply voltage (v dd C v ee ) ...................... C0.3v to 100v pwrgd , pwrgd pins ............................. C0.3v to 100v sense, gate pins ..................................... C0.3v to 20v uv, ov pins ................................................ C0.3v to 60v drain pin ................................................... C2v to 100v maximum junction temperature ........................... 125c (note 1), all voltages referred to v ee 1 2 3 4 8 7 6 5 top view v dd drain gate sense pwrgd ov uv v ee n8 package 8-lead pdip s8 package 8-lead plastic so t jmax = 125c, ja = 120c/w (n8) t jmax = 125c, ja = 150c/w (s8) 1 2 3 4 8 7 6 5 top view v dd drain gate sense pwrgd ov uv v ee n8 package 8-lead pdip s8 package 8-lead plastic so t jmax = 125c, ja = 120c/w (n8) t jmax = 125c, ja = 150c/w (s8) order information operating temperature range lt4250lc/lt4250hc ............................... 0c to 70c lt4250li/lt4250hi .............................. C40c to 85c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c lead free finish tape and reel part marking package description temperature range lt4250lcn8#pbf lt4250lcn8#trpbf 4250l 8-lead pdip 0c to 70c lt4250lcs8#pbf lt4250lcs8#trpbf 4250l 8-lead plastic so 0c to 70c lt4250lin8#pbf lt4250lin8#trpbf 4250li 8-lead pdip C40c to 85c lt4250lis8#pbf lt4250lis8#trpbf 4250li 8-lead plastic so C40c to 85c lt4250hcn8#pbf lt4250hcn8#trpbf 4250h 8-lead pdip 0c to 70c lt4250hcs8#pbf lt4250hcs8#trpbf 4250h 8-lead plastic so 0c to 70c lt4250hin8#pbf lt4250hin8#trpbf 4250hi 8-lead pdip C40c to 85c lt4250his8#pbf lt4250his8#trpbf 4250hi 8-lead plastic so C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
lt4250l/lt4250h 3 4250lhfa electrical characteristics symbol parameter conditions min typ max units dc v dd supply voltage operating range l 18 80 v i dd supply current uv = 3v, ov = v ee , sense = v ee l 1.6 5 ma v uvl undervoltage lockout 15.4 v v cl current limit trip voltage v cl = (v sense C v ee ) l 40 50 60 mv i pu gate pin pull-up current gate drive on, v gate = v ee l C30 C45 C60 a i pd gate pin pull-down current gate drive off 24 50 70 ma i sense sense pin current v sense = 50mv C20 a v gate external gate drive (v gate C v ee ), 18v v dd 80v l 10 13.5 18 v v uvh uv pin high threshold voltage uv increasing l 1.24 1.255 1.27 v v uvl uv pin low threshold voltage uv decreasing l 1.105 1.125 1.145 v v uvhy uv pin hysteresis 130 mv i inuv uv pin input current v uv = v ee l C0.02 C0.5 a v ovh ov pin high threshold voltage ov increasing l 1.235 1.255 1.275 v v ovl ov pin low threshold voltage ov decreasing l 1.21 1.235 1.255 v v ovhy ov pin hysteresis 20 mv i inov ov pin input current v ov = v ee l C0.03 C0.5 a v dl drain low threshold v drain C v ee , drain decreasing 1.1 1.6 2.3 v v gh gate high threshold v gate C v gate decreasing 1.3 v i drain drain input bias current v drain = 48v l 10 80 500 a v ol pwrgd output low voltage pwrgd (lt4250l), (v drain C v ee ) < v dl i out = 1ma i out = 5ma l l 0.48 1.2 0.8 3 v v pwrgd output low voltage (pwrgd C drain) pwrgd (lt4250h), v drain = 5v i out = 1ma l 0.75 1v i oh output leakage pwrgd (lt4250l), v drain = 48v, v pwrgd = 80v pwrgd (lt4250h), v drain = 0v, v pwrgd = 80v l l 0.05 0.05 10 10 a a ac t phlov ov high to gate low figures 1a, 2 1.7 s t phluv uv low to gate low figures 1a, 3 1.5 s t plhov ov low to gate high figures 1a, 2 5.5 s t plhuv uv high to gate high figures 1a, 3 6.5 s t phlsense sense high to gate low figures 1a, 4a 1 3 s t phlcb current limit to gate low figures 1b, 4b 500 s t phldl drain low to pwrgd low drain low to (pwrgd C drain) high (lt4250l) figures 1a, 5a (lt4250h) figures 1a, 5a 1 1 s s t phlgh gate high to pwrgd low gate high to (pwrgd C drain) high (lt4250l) figures 1a, 5b (lt4250h) figures 1a, 5b 1.5 1.5 s s the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 2), v dd = 48v, v ee = 0v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise speci? ed.
lt4250l/lt4250h 4 4250lhfa typical performance characteristics gate voltage vs temperature current limit trip voltage vs temperature gate pull-up current vs temperature gate pull-down current vs temperature pwrgd output low voltage vs temperature (lt4250l) pwrgd output impedance vs temperature (lt4250h) supply current vs supply voltage supply current vs temperature gate voltage vs supply voltage supply voltage (v) 0 supply current (ma) 1.3 1.4 1.5 60 100 4250 g01 1.2 1.1 0 20 40 80 1.6 1.7 1.8 t a = 25c temperature (c) C50 C25 1.0 supply current (ma) 1.1 1.2 1.3 1.4 1.6 0255075 4250 g02 100 1.5 v dd = 48v supply voltage (v) 0 6 gate voltage (v) 7 9 10 11 40 80 100 15 4250 g03 8 20 60 12 13 14 t a = 25c temperature (c) 12.0 gate voltage (v) 13.0 14.0 15.0 12.5 13.5 14.5 C25 0 75 4250 g04 100 C50 25 50 v dd = 48v temperature (c) C50 48 trip voltage (mv) 49 51 52 53 55 25 0 50 4250 g05 50 54 100 C25 75 temperature (c) C50 gate pull-up current (a) 48 47 46 45 44 43 42 41 40 75 4250 g06 C25 100 50 25 0 v gate = 0v temperature (c) C50 gate pull-down current (ma) 49 52 55 75 4250 g07 46 43 40 C25 0 25 50 100 v gate = 2v temperature (c) C50 pwrgd output low voltage (v) 0.3 0.4 0.5 75 4250 g08 0.2 0.1 0 C25 25 0 50 100 i out = 1ma temperature (c) C50 2 output impedance (k) 3 4 5 6 7 8 C25 25 05075 4250 g09 100 v drain C v ee > 2.4v
lt4250l/lt4250h 5 4250lhfa pin functions for this pin is 1.5s. add an external capacitor to this pin for additional filtering. v ee (pin 4): negative supply voltage input. connect to the lower potential of the power supply. sense (pin 5): circuit breaker sense pin. with a sense resistor placed in the supply path between v ee and sense, the overcurrent condition will pull down the gate pin and regulate the voltage across the resistor to be 50mv. if the overcurrent condition exists for more than 500s the electronic circuit breaker will trip and turnoff the external mosfet. if the current limit value is set to twice the normal operating current, only 25mv is dropped across the sense resistor during normal operation. to disable the current limit feature, v ee and sense can be shorted together. gate (pin 6): gate drive output for the external n-channel mosfet. the gate pin will go high when the following start-up conditions are met: the uv pin is high, the ov pin is low, (v sense C v ee ) < 50mv and the v dd pin is greater than v uvloh . the gate pin is pulled high by a 45a cur- rent source and pulled low with a 50ma current source. during current limit the gate pin is pulled low using a 100ma current source. drain (pin 7): analog drain sense input. connect this pin to the drain of the external n-channel mosfet and the v C pin of the power module. when the drain pin is below v dl , the pwrgd /pwrgd pin will latch to indicate the switch is on. v dd (pin 8): positive supply voltage input. connect this pin to the higher potential of the power supply inputs and the v + pin of the power module. an undervoltage lockout circuit disables the chip until the v dd pin is greater than the 16v v uvloh threshold. pwrgd /pwrgd (pin 1): power good output pin. this pin will latch a power good indication when v drain is within v dl of v ee and v gate is within v gh of v gate . this pin can be connected directly to the enable pin of a power module. when the drain pin of the lt4250l is above v ee by more than v dl or v gate is more than v gh from v gate , the pwrgd pin will be high impedance, allowing the pull-up current of the modules enable pin to pull the pin high and turn the module off. when v drain drops below v dl and v gate rises above v gh , the pwrgd pin sinks current to v ee , pulling the enable pin low and turning on the module. this condition is latched until the gate pin is turned off via the uv, ov, uvlo or the electronic circuit breaker. when the drain pin of the lt4250h is above v ee by more than v dl or v gate is more than v gh from v gate , the pwrgd pin will sink current to the drain pin which pulls the modules enable pin low, forcing it off. when v drain drops below v dl and v gate rises above v gh , the pwrgd sink current is turned off, allowing the modules pull-up current to pull the enable pin high and turn on the module. this condition is latched until the gate pin is turned off via the uv, ov, uvlo or the electronic circuit breaker. ov (pin 2): analog overvoltage input. when ov is pulled above the 1.255v threshold, an overvoltage condition is detected and the gate pin will be immediately pulled low. the gate pin will remain low until ov drops below the 1.235v threshold. uv (pin 3): analog undervoltage input. when uv is pulled below the 1.125v threshold, an undervoltage condition is detected and the gate pin will be immediately pulled low. the gate pin will remain low until uv rises above the 1.255 threshold. the uv pin is also used to reset the electronic circuit breaker. if the uv pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. the response time
lt4250l/lt4250h 6 4250lhfa block diagram C + C + + C + C drain 4250 bd gate sense v ee v ee v dl output drive pwrgd /pwrgd 50mv v cc v dd ref ref uv ov logic v cc and reference generator C + C + C + + C v gate v gh 500s delay gate driver uvlo
lt4250l/lt4250h 7 4250lhfa test circuit timing diagram pwrgd /pwrgd v dd v + 5v ov v drain 48v r 5k drain lt4250l/lt4250h uv gate v ee sense v sense 4250 f01a v uv v ov + C pwrgd /pwrgd v dd ov 48v 20v drain lt4250l/lt4250h uv gate v ee sense 4250 f01b v uv 0.1f + C + C 10k 10 10 irf530 figure 1a. test circuit 1 figure 1b. test circuit 2 2v 1v 4250 f02 t phlov 1.255v 0v ov gate 1v 1.235v t plhov 2v 1v 4250 f03 t phluv 1.125v 0v uv gate 1v 1.255v t plhuv 1v 4250 f04a t phlsense 60mv sense gate 100mv v ee 1v 4250 f04b t phlcb uv gate 1v 4250 f05a v pwrgd C v drain = 0v drain pwrgd 1v 1.4v v ee drain pwrgd 1v 1.4v t phldl t phldl v ee v ee 4250 f05b v pwrgd C v drain = 0 gate pwrgd 1v 1.4v 1.4v v ee gate pwrgd 1v t phlgh t phlgh v gate C v gate = 0 v gate C v gate = 0 figure 2. ov to gate timing figure 3. uv to gate timing figure 4a. sense to gate timing figure 4b. active current limit timeout figure 5a. drain to pwrgd /pwrgd timing figure 5b. gate to pwrgd /pwrgd timing
lt4250l/lt4250h 8 4250lhfa applications information figure 6a. inrush control circuitry figure 6b. inrush control waveforms hot circuit insertion when circuit boards are inserted into a live C48v back- plane, the bypass capacitors at the input of the boards power module or switching power supply can draw huge transient currents as they charge up. the transient currents can cause permanent damage to the boards components and cause glitches on the system power supply. the lt4250 is designed to turn on a boards supply volt- age in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the chip also provides undervoltage, overvoltage and overcurrent pro- tection while keeping the power module off until its input voltage is stable and within tolerance. power supply ramping the input to the power module on a board is controlled by placing an external n-channel pass transistor (q1) in the power path (figure 6a). r1 provides current fault detection and r2 prevents high frequency oscillations. resistors r4, r5 and r6 provide undervoltage and over-voltage sensing. by ramping the gate of q1 up at a slow rate, the inrush current charging load capacitors c3 and c4 can be limited to a safe value when the board makes connection. resistor r3 and capacitor c2 act as a feedback network to accurately control the inrush current. the c2 capacitor can be calculated with the following equation: c2 = (45a ? c l )/i inrush where c l is the total load capacitance = c3 + c4 + module input capacitance. capacitor c1 and resistor r3 prevent q1 from momentarily turning on when the power pins first make contact. without c1 and r3, capacitor c2 would pull the gate of q1 up to a voltage roughly equal to v ee ? c2/cgs(q1) before the lt4250 could power up and actively pull the gate low. by placing capacitor c1 in parallel with the gate capacitance of q1 and isolating them from c2 using resistor r3 the problem is solved. the value of c1 is given by: c1 = v inmax v th v t h ? c2 + c gd () c1 ? 35 ? c2 for v inmax = 72v where v th is the mosfets minimum gate threshold and v inmax is the maximum operating input voltage. r3 should not exceed a value that produces an r3 ? c2 time-constant of 150s. a 1k value for r3 will ensure this for c2 values up to 150nf. the waveforms are shown in figure 6b. when the power pins make contact, they bounce several times. while the contacts are bouncing, the lt4250 senses an undervoltage condition and the gate is immediately pulled low when the power pins are disconnected. once the power pins stop bouncing, the gate pin starts to ramp up. when q1 turns on, the gate voltage is held constant by the feedback network of r3 and c2. when the + v ee v dd lt4250h pwrgd uv = 38.5v ov = 71v sense c1 470nf 25v c3 0.1f 100v c4 100f 100v c5 100f 16v q1 irf530 r2 10 5% r3 1k, 5% c2 15nf 100v r4 549k 1% r5 6.49k 1% r6 10k 1% r1 0.02 5% 4 3 2 ov C48v rtn C48v rtn (short pin) C48v uv 56 8 7 1 gate drain vicor vi-j30-cy v out + v out C v in + 5v 4250 f06a gate in v in C + * * diodes inc. smat70a 4 3 2 1 inrush current 500ma/div gate Cv ee 10v/div drain 50v/div v ee 50v/div 25ms/div 4250 f06b contact bounce module turn-on module turn-on contact bounce
lt4250l/lt4250h 9 4250lhfa drain voltage has finished ramping, the gate pin then ramps to its final value. current limit/electronic circuit breaker the lt4250 features a current limit function that protects against short circuits or excessive supply currents. if the current limit is active for more than 500s the electronic circuit breaker will trip. by placing a sense resistor between the v ee and sense pin, the current limit will be activated whenever the voltage across the sense resistor is greater than 50mv. note that the current limit threshold should be set suffi- ciently high to account for the sum of the load current and the inrush current. the maximum value of the inrush current is given by: i inrush 0.8 ? 40mv r sens e ?i load, where the 0.8 factor is used as a worst case margin com- bined with the minimum trip voltage (40mv). in the case of a short circuit, the current limit circuitry activates and immediately pulls the gate low, servos the sense voltage to 50mv, and starts a 500s timer. the mosfet current is limited to 50mv/r sense (see figure 7). if the short circuit persists for more than 500s, the circuit breaker trips and pulls the gate pin low, shutting off the mosfet. the circuit breaker is reset by pulling uv low, or by cycling power to the part. if the short circuit clears before the 500s timing interval the current limit will deactivate and release the gate. applications information figure 7. short-circuit protection waveforms drain 50v/div gate 10v/div i d (q1) 5a/div 1ms/div the lt4250 guards against voltage steps on the input supply. a positive voltage step (increasing in magnitude) on the input supply causes an inrush current that is proportional to the voltage slew rate i = c l ? v/ t. if the inrush exceeds 50mv/r sense , the current limit will activate as shown in figure 8. the gate pin pulls low, limiting the current to 50mv/r sense . at this level the mosfet drain will not follow the source as the input voltage rapidly changes, but instead remains at the voltage stored on the load capacitance. the load capacitance begins to charge at a current of 50mv/r sense , but not for long. as the load capacitance charges, c2 pushes back on the gate and limits the mosfet current in a manner identical to the initial start- up condition which is less than the short circuit limiting value of 50mv/r sense . thus the circuit breaker does not trip. to ensure correct operation under input voltage step conditions, r sense must be chosen to provide a current limit value greater than the sum of the load current and the dynamic current in the load capacitance. for c2 values less than 10nf a positive voltage step increasing in magnitude on the input supply can result in the q1 turning off momentarily due to current limit overshoot which can shut down the output. by adding an additional resistor and diode, q1 remains on during the voltage step. this is shown as d1 and r7 in figure 9. the purpose of d1 is to shunt current around r7 when the power pins first make contact and allow c1 to hold the gate low. the value of r7 should be sized to generate an r7 ? c1 time constant of 33s. under some conditions, a short circuit at the output can cause the input supply to dip below the uv threshold. the lt4250 turns off once and then turns on until the electronic circuit breaker is tripped. this can be minimized by adding a deglitching delay to the uv pin with a capacitor from uv to v ee . this capacitor forms an rc time constant with the resistors at uv, allowing the input supply to recover before the uv pin resets the circuit breaker.
lt4250l/lt4250h 10 4250lhfa figure 8. voltage step on input supply waveforms applications information figure 9. circuit for input steps with small c2 (<10nf) figure 10. automatic restart after current fault v ee and drain 20v/div i d (q1) 5a/div 500s/div 4250 08 v ee v dd lt4250h pwrgd sense c1 150nf 25v c3 0.1f 100v c4 22f 100v q1 irf530 r2 10 5% r3 1k 5% c2 3.3nf 100v r4 549k 1% r5 6.49k 1% r6 10k 1% r1 0.02 5% 4 3 2 C48v rtn C48v ov uv 56 8 1 gate drain 4250 f09 + 7 C48v rtn (short pin) * * diodes inc. smat70a r7 220 5% 4 3 2 1 d1 bat85 v ee v dd lt4250l pwrgd sense c1 470nf 25v c4 1f 100v c3 100f 100v q1 irf530 r2 10 5% r8 510k 5% r3 1k, 5% c2 15nf 100v r4 549k 1% r7 1m 5% r5 16.5k 1% r9 10k 1% r6 549k 1% q3 zvn3310 q2 2n2222 d1 1n4148 r1 0.02 5% 4 3 2 ov C48v uv 56 8 7 1 gate drain 4250 f10a 3 2 + C48v rtn C48v rtn (short pin) * * diodes inc. smat70a 4 3 2 1 node 2 50v/div gate 2v/div 1s/div 4250 f10 a circuit that automatically resets the circuit breaker after a current fault is shown in figure 10. transistors q2 and q3 along with r7, r8, c4 and d1 form a programmable one-shot circuit. before a short occurs, the gate pin is pulled high and q3 is turned on, pulling node 2 to v ee . resistor r8 turns off q2. when a short occurs, the gate pin is pulled low and q3 turns off. node 2 starts to charge c4 and q2 turns on, pulling the uv pin low and resetting the circuit breaker. as soon as c4 is fully charged, r8 turns off q2, uv goes high and the gate starts to ramp up. q3 turns back on and quickly pulls node 2 back to v ee . diode d1 clamps node 3 one diode drop below v ee . the duty cycle is set to 10% to prevent q1 from overheating.
lt4250l/lt4250h 11 4250lhfa applications information undervoltage and overvoltage detection the uv (pin 3) and ov (pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power sup- ply input. the uv and ov pins are internally connected to analog comparators with 130mv and 20mv of hysteresis respectively. when the uv pin falls below its threshold or the ov pin rises above its threshold, the gate pin is im- mediately pulled low. the gate pin will be held low until uv is high and ov is low. the undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in figure 11. with r4 = 549k, r5 = 6.49k and r6 = 10k, the undervoltage threshold is set to 38.5v (with a 43v release from undervoltage) and the overvoltage threshold is set to 71v. the resistor divider will also gain up the hysteresis at the uv pin and ov pin to 4.5v and 1.2v at the input respectively. pwrgd /pwrgd output the pwrgd /pwrgd output can be used to directly enable a power module when the input voltage to the module is within tolerance. the lt4250l has a pwrgd output for modules with an active low enable input, and the lt4250h has a pwrgd output for modules with an active high enable input. when the drain voltage of the lt4250h is high with respect to v ee (figure 12) or the gate voltage is low, the internal transistor q3 is turned off and i 1 and q2 clamp the pwrgd pin one sat drop (0.3v) above the drain pin.transistor q2 sinks the modules pull-up current and the module turns off. when the drain voltage drops below v dl and the gate voltage is high, q3 will turn on, shorting the bottom of i 1 to drain and turning q2 off. the pull-up current in the module pulls the pwrgd pin high and enables the module. when the drain voltage of the lt4250l is high with respect to v ee or the gate voltage is low, the internal pull-down transistor q2 is off and the pwrgd pin is in a high impedance state (figure 13). the pwrgd pin will be pulled high by the modules internal pull-up current source, turning the module off. when the drain voltage drops below v dl and the gate voltage is high, q2 will turn on and the pwrgd pin will pull low, enabling the module. the pwrgd signal can also be used to turn on an led oroptoisolator to indicate that the power is good as shown in figure 14. gate pin voltage regulation when the supply voltage to the chip is more than 18v, the gate pin voltage is regulated at 13.5v above v ee . the gate voltage will be no greater than 18v for supply voltages up to 80v. v ee v dd lt4250l/lt4250h r4 r5 r6 4 4250 f11 ov C48v rtn 3 2 C48v uv 8 v uv = 1.255 r4 + r5+ r6 r5 + r6 () v ov = 1.255 r4 + r5+ r6 r6 () C48v rtn (short pin) + v ee v dd lt4250h sense c1 c3 q1 r2 r3 c2 r4 r5 r6 r1 4 3 2 ov C48v rtn C48v uv 56 8 1 7 gate 4250 f12 pwrgd drain v ee q3 active high enable module v out + v out C v in + v in C on/off C48v rtn (short pin) * * diodes inc. smat70a 4 3 2 1 q2 v dl v gh + C + C + C + C gate v gate i 1 figure 11. undervoltage and overvoltage sensing figure 12. active high enable module
lt4250l/lt4250h 12 4250lhfa applications information figure 13. active low enable module figure 14. using pwrgd to drive an optoisolator v ee lt4250l sense ov uv v dl v gh + C + C + C + C gate v gate + v dd c1 c3 q1 r2 r3 c2 r4 r5 r6 r1 4 3 2 C48v rtn C48v 56 8 1 7 gate 4250 f13 pwrgd drain v ee active low enable module v out + v out C v in + v in C on/off C48v rtn (short pin) * * diodes inc. smat70a 4 3 2 1 q2 v ee v dd lt4250l pwrgd sense c1 470nf 25v c3 100f 100v q1 irf530 r2 10 5% r7 51k 5% r3 1k, 5% c2 15nf 100v r4 549k 1% r5 6.49k 1% r6 10k 1% r1 0.02 5% 4 3 2 ov C48v rtn C48v uv 56 8 7 1 moc207 gate drain 4250 f14 pwrgd + C48v rtn (short pin) * * diodes inc. smat70a 4 3 2 1
lt4250l/lt4250h 13 4250lhfa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description n8 package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) n8 1002 .065 (1.651) typ .045 C .065 (1.143 C 1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 .015* (6.477 0.381) .400* (10.160) max .008 C .015 (0.203 C 0.381) .300 C .325 (7.620 C 8.255) .325 +.035 C.015 +0.889 C0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
lt4250l/lt4250h 14 4250lhfa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt 0309 rev a ? printed in usa related parts typical application part number description comments lt c ? 1421 dual hot swap controller with additional C12v control operates from 3v to 12v ltc1422 hot swap controller in so-8 system reset output with programmable delay lt1640ah/lt1640al C48v hot swap controller in so-8 lt4250 is a pin-compatible upgrade to lt1640 lt1641-1/lt1641-2 48v hot swap controller in so-8 foldback current limit, 9v to 80v, auto-retry/latch-off ltc1642 fault protected hot swap controller operates up to 16.5v, protected to 33v ltc1643 pci hot swap controller 3.3v, 5v, 12v, C12v supplies for pci bus ltc1645 dual hot swap controller operates from 1.2v to 12v, power sequencing ltc1646 dual compactpci hot swap controller 3.3v, 5v supplies with precharge and local pci reset logic ltc1647 dual hot swap controller dual on pins for supplies from 3v to 15v ltc4211 hot swap controller with multifunction current control 2.5v to 16.5v supplies, active inrush current limiting ltc4251 C48 hot swap controller in sot-23 active current limiting, fast comparator for catastrophic faults ltc4252 C48 hot swap controller in msop active current limiting, fast comparator for catastrophic faults, separate uv/0v pins, power-good output figure 15. typical application using a filter module + v ee v dd lt4250l pwrgd sense c1 470nf 25v c2 15nf 100v c3 0.1f 100v c4 0.1f 100v c6 0.1f 100v c5 100f 100v c7 100f 16v q1 irf530 r2 10 5% r3 1k 5% r4 549k 1% r5 6.49k 1% r6 10k 1% r1 0.02 5% 4 ov C48v rtn 3 2 C48v uv 5 6 8 7 1 gate drain lucent jw050a1-e v out + sense + trim sense C v out C v in + 9 5v 4250 f15 8 7 6 5 3 1 2 4 on /off case v in C v out + v out C v in + case v in C + lucent fltr100v10 C48v rtn (short pin) * * diodes inc. smat70a 4 3 2 1 moc207 r7 51k 5% 1n4003 using an emi filter module many applications place an emi filter module in the powerpath to prevent switching noise of the module from being injected back onto the power supply. a typical application using the lucent fltr100v10 filter module is shown in figure 15. when using a filter, an optoisolator is required to prevent common mode transients from destroying the pwrgd and on /off pins.

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